1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and its circuit designing system and, in particular, to a circuit designing system using a gated clock circuit and a computer aided design (CAD).
2. Description of the Related Art
As the technique for achieving the lower power dissipation of a semiconductor integrated circuit (LSI), a gated clock circuit has been put to practical use which has a tree structure of buffer circuit groups. This gated clock circuit is controlled by an enable signal to allow a clock signal for synchronization operation to be selectively supplied to a portion of a load circuit group through a portion of the buffer circuit groups in the tree structure.
FIG. 8 is a block circuit showing an example of a conventional gated clock circuit. In the gated clock circuit, a clock signal clk for synchronization operation is supplied to load circuit groups (for example, flip-flop circuit groups) through initial to final stages (in this example, through three stages) of buffer circuit groups in a tree structure. A two-branch structure of buffer circuit groups is shown in FIG. 8.
The clock signal clk is input to a buffer 11 in an initial stage (first branch stage) and an output clk1 of the buffer 11 is inputted to buffers 12, 13 in a subsequent stage. An output clk2 of the buffer 12 is inputted to buffers 14, 15 in a subsequent stage (second branch stage). The output clk3 of the buffer 14 is supplied to one input of each of enable-signal-controlled AND buffers (gated AND buffers) 16, 17 in a subsequent stage (third branch stage).
The enable-signal-controlled AND buffer 16 receives, as the other input, an output enout1 of a negative edge latch circuit 18 which receives an enable signal en1 and clock signal CLK. An output gclk1 of the enable-signal-controlled AND buffer 16 is supplied as a clock input to a first flip-flop circuit (F/F1) group.
The enable-signal-controlled AND buffer 17 receives, as the other input, an output enout2 of a negative edge latch circuit 19 which receives an enable signal en2 and clock signal. An output gclk2 of the enable-signal-controlled AND buffer 17 is supplied as a clock input to a second flip-flop circuit (F/F2) group.
It is to be noted that, when the clock signal CLK is in a “L” level, the negative edge latch circuits 18, 19 allow corresponding enable signals en1, en2 to pass through and, when the clock signal CLK is in a “H” level, these negative edge latch circuits 18, 19 hold the corresponding enable signals en1, en2. By doing so, it is possible to prevent any operation error caused by a whisker-like input noise of the clock signal CLK.
It is also to be noted that, as in the case of a system of the buffer 14, enable-signal-controlled AND buffers 20, 21 are connected to the load side of the buffer 15 of the second branch stage and, to the enabling buffers 20, 21, negative edge latch circuits 22, 23 and flip-flop circuit F/F3 and F/F4 groups are connected respectively.
The output clk4 of the buffer 15 is supplied to one input of each of enable-signal-controlled AND buffers (gated AND buffers) 20, 21 in a subsequent stage (third branch stage).
The enable-signal-controlled AND buffer 20 receives, as the other input, an output enout3 of a negative edge latch circuit 22 which receives an enable signal en3 and clock signal CLK. An output gclk3 of the enable-signal-controlled AND buffer 20 is supplied as a clock input to a third flip-flop circuit (F/F3) group.
The enable-signal-controlled AND buffer 21 receives, as the other input, an output enout4 of a negative edge latch circuit 23 which receives an enable signal en4 and clock signal. An output gclk4 of the enable-signal-controlled AND buffer 21 is supplied as a clock input to a fourth flip-flop circuit (F/F4) group.
It is to be noted that, when the clock signal CLK is in a “L” level, the negative edge latch circuits 22, 23 allow corresponding enable signals en3, en4 to pass through and, when the clock signal CLK is in a “H” level, these negative edge latch circuits 18, 19 hold the corresponding enable signals en3, en4. By doing so, it is possible to prevent any operation error caused by a whisker-like input noise of the clock signal CLK.
FIG. 9 is a timing chart showing a practical operation (signals) of the circuit shown in FIG. 8. When the output enout1 of the latch circuit 18 is in a “1” state, the output gclk1 of the enable-signal-controlled AND buffer 16 is activated and, with the same operation as that of the clock signal clk, data is loaded to the first flip-flop circuit (F/F1) group. When, on the other hand, the output enout1 of the latch circuit 18 is in a “0” state, the output gclk1 of the enable-signal-controlled AND buffer 16 is deactivated and the F/F1 group is not supplied with a clock so that it is not operated. Since, at this time, no clock is supplied to the F/F1 group, the gated clock circuit becomes lower in power dissipation than an ordinary circuit.
When the output enout2 of the latch circuit 19 is in “1” state, the output gclk2 of the enable-signal-controlled AND buffer 17 is activated and, with the same operation as the lock signal clk, data is loaded to the second flip-flop circuit (F/F2) group. When the output enout2 of the latch circuit 19 is in a “0” state, the output glk2 of the enable-signal-controlled AND buffer 17 is deactivated and the F/F2 group is not supplied with a clock so that it is not operated. Therefore, the gated clock circuit becomes lower in power dissipation than the ordinary circuit.
In the circuit shown in FIG. 8, on the other hand, the output clk3 of the buffer 14 in the preceding stage (second branch stage) of the enable-signal-controlled AND buffers 16, 17 continues ON as in the case of the input clock clk.
It is functionally sufficient, however, that, only when the output enout1 of the latch circuit 18 or the output enout2 of the latch circuit 19 is in the “1” state, the output clk3 of the buffer 14 performs the same operation as the input clock clk. In other word, when the output enout1 of the latch circuit 18 and output enout2 of the latch circuit 19 are both in the “0” state, the output clock clk3 of the buffer 14 needs not operate in the same way as the input clock.
However, in the circuit shown in FIG. 8, the output clock clk3 of the buffer 14 continues ON as in the same way as the input clock clk, even when the output enout1 of the latch circuit 18 and output enout2 of the latch circuit 19 are both in the “0” state. As the result, there occurs a wasteful power dissipation.
As set out above, in the gate clock circuit using the buffer circuit groups in the conventional tree structure, even when there is no need to supply the clock to a buffer circuit closer to the load circuit side (leaf side), another buffer circuit closer to a root side than said buffer circuit normally continues ON, thus involving a wasteful power dissipation problem.